1. Field of the Invention
The present invention generally relates to integrated circuits, and more particularly to measuring the spacing between metal lines.
2. Background of Invention
Semiconductor devices are used in many electronic and other applications. Semiconductor devices comprise integrated circuits that are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, and patterning the thin films of material to form the integrated circuits.
Metallization layers are usually the top-most layers of semiconductor devices. The manufacturing of semiconductor devices is typically classified into two phases, the front end of line (FEOL) and the back end of line (BEOL). The BEOL is typically considered to be the point of the manufacturing process where metallization layers are formed, and FEOL is considered to include the manufacturing processes prior to the formation of metallization layers, and where active devices are formed.
While some integrated circuits have a single top layer of metallization, other integrated circuits comprise multi-level interconnects, wherein two or more metallization layers are formed over a semiconductor wafer or workpiece. Each metallization layer typically comprises a plurality of metal lines separated from one another by an insulating material, also referred to as an inter-level dielectric (ILD). The metal lines in immediately neighboring horizontal metallization layers may be connected vertically in predetermined places by vias formed between the metal lines.
One of the characteristics affecting the reliability of semiconductor devices may be the top-to-top spacing (“spacing”) between metal lines. The spacing may be defined as the distance between two adjacent metal lines as measured from the edges. Therefore, it may be desirable to measure the spacing between metal lines on every die. Current methods of obtaining the spacing measurement may include scanning electron microscope (SEM) inspection and electrical testing. The SEM inspection may take valuable time during fabrication, and the electrical testing may not provide accurate and repeatable results.
Any SEM inspection may occur immediately after a polishing technique, but before a dielectric cap may be deposited on top of the metallization layer being inspected. Further, SEM inspection may take an unacceptable amount of time during fabrication, delaying the formation of the dielectric cap and allowing copper dendrites to grow on the exposed metal lines. The copper dendrites may ultimately affect the reliability of the semiconductor device.
Also, electrical measuring techniques known in the art may be used to obtain the spacing measurement. Current electrical measurement techniques may include capacitance and resistance measurements. Capacitance measurement results may, however, be difficult to interpret because they are affected by the height and sidewall angle of the metal lines as well as the spacing. Similar difficulties may be experienced with resistance measurements.
Therefore, a need exists for a method to accurately obtain the spacing between metal lines without the difficulties identified above.